今天使用課本第七頁的範例測試
範例:
程式碼:
module top;
system_clock #100 clock1(A);
system_clock #200 clock2(B);
system_clock #400 clock3(SEL);
mux m1(OUT, A, B, SEL);
endmodule
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
時脈圖:
讚
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